1. Field of the Invention
The present invention relates to a driving device, particularly to a high load driving device.
2. Description of the Related Art
Refer to FIG. 1 for a conventional high load driving circuit, which comprises an inverter 10, two capacitors 12, 14, four P-type field-effect transistors (FET) 16, 18, 20, 22, and four N-type field-effect transistors 24, 26, 28, 30. When the input voltage Vi is equal to a ground potential, the voltage Va output by the inverter 10 is Vdd. The drain voltage V2p of the third N-type FET 28 is fixedly set to the ground potential by the turned-on third N-type FET 28. Thus, the first capacitor 12 has a given voltage and stores a given quantity of charges. Meanwhile, Va is coupling the second capacitor 14 to push up the drain voltage V2n of the second P-type FET 18 to be greater than Vdd. Then, the turned-on third P-type FET 20 makes the gate voltage V1n of the fourth N-type FET 30 greater than Vdd. Consequently, the fourth N-type FET 30 has increased capability of driving the current of a load 32. When the input Vi is equal to Vdd, the voltage Va output by the inverter 10 is equal to the ground potential. The drain voltage V2n of the second P-type FET 18 is fixedly set to Vdd by the turned-on second P-type FET 18. Thus, the second capacitor 14 has a given voltage and stores a given quantity of charges. Meanwhile, Va is coupling the first capacitor 12 to pull down the drain voltage V2p of the third N-type FET 28 to be lower than the ground potential. Then, the turned-on second N-type FET 26 makes the gate voltage V1p of the fourth P-type FET 22 smaller than the ground potential. Consequently, the fourth P-type FET 22 has increased capability of driving the current of a load 32. Thereby, the two capacitors can alternately stores charges and respectively push up and pull down V2n and V2p to the required high-level voltage and low-level voltage according to the input voltage Vi. Thus, the conventional high load driving circuit can provide higher current than the original driving transistors.
In the abovementioned prior art, the coupled capacitors perform step-up and step-down to attain the required over-Vdd high-level voltage and under-ground potential low-level voltage. However, current is likely to leak out from the turned-on second P-type FET 18 and the turned-on third N-type FET 28. Thus, the voltage level is decreased. When the input voltage Vi is equal to a ground potential, Va is coupling the second capacitor 14 to push up the drain voltage V2n of the second P-type FET 18 to be greater than Vdd, and the turned-on third P-type FET 20 makes the fourth N-type FET 30 have a gate voltage V1n greater than Vdd and have an increased capability of driving the current of the load 32. However, V2n, which is over Vdd, creates a positive bias on the second P-type FET 18 with respect to the Va node, which is at Vdd. Thus is formed a current-leakage path toward the power source Vdd. The current leakage decreases the level of the over-Vdd voltage of V1n and V2n. When Vi is equal to Vdd, Va is equal to the ground potential. Meanwhile, Va is coupling the first capacitor 12 to pull down the drain voltage V2p of the third N-type FET 28 to be lower than the ground potential, and the turned-on second N-type FET 26 makes the fourth P-type FET 22 have a gate voltage V1p smaller than the ground potential and have an increased capability of driving the current of the load 32. However, the voltage difference, between V2p (below the ground potential) and Va (at the ground potential), will turn on the third N-type FET 28 and cause current leakage from the ground potential to V2p. The current leakage decreases the level of the below-ground voltage of V1p and V2p. Thus is degraded the performance of the high load driving circuit.
Therefore, the present invention proposes a high load driving device to solve the conventional problems.